Experiments of the third kind... This is an attempt at making a faithful and accurate HDL implementation of CADR. There will be no attempt at making this synthesizable (at this time)!
There is a IRC channel on irc.libera.net, ##lispm for random chit-chat. Feel free to send bugs directly to ams@gnu.org.
- Git
- GNU Make
- Python 3
- a C compiler (for the netlist extractor and the cosimulation libraries)
- GHDL with the GCC or LLVM code generator or NVC
- optionally some sort of FST/VCD viewer:
Makefile is divided into three parts; Makefile.config and Makefile.common are always used.
Makefile.ghdl and Makefile.nvc are used depending on the value of the CADR4_HDLCOMPILER variable (ghdl or nvc). Default is ghdl.
git clone https://github.com/ams/cadr4
cd cadr4
make
All build artifacts are created under build directory.
Two special testbenches cadr_tb and cadr_boot_tb are autogenerated by make (build/cadr_tb.vhd and build/cadr_boot_tb.vhd); they connect every page of CADR, ICMEM and BUSINT by signal name. cadr_boot_tb also pulses -lm boot so the CADR boots from the PROM.
make run-cadr_tb
make run-cadr_boot_tb
CADR4_STOPTIME=200us make check-boot # the same, bounded
The diagnostic display (5x 7-segment LED displays with dot) is printed on the console by the cosimulation library, which is loaded only for these two testbenches. The boot run stops by itself when the PROM reaches 0313 (the first main memory access).
make check
runs every unit testbench (ttl, dip, helper and the cadr page tests in cadr_test) and stops at the first failure. make check-ttl, check-dip, check-helper and check-cadr run one group; make run-X runs a single testbench.
Testbenches fail with assert ... severity error; both simulators are run with that as the exit severity, so informational reports are fine.
make regen
regenerates the packages, the page entities and the suds architectures from the drawings. Run it after changing anything in dip/, helper/, a ttl/ entity, a rom/*.table or *.rename file or the generator scripts; git diff must then show only the intended changes. CI checks that the committed generated files are current.
This is only applicable when GHDL is used.
If there is a wave.opt file at the project root, it is used as waveform options file in GHDL (--read-wave-opt).
If the file contains "recreate" in its first line, the file is deleted and recreated. This will show all signal paths.
If the file contains "ignore" in its first line, the file is ignored, --read-wave-opt is not used.
This is only applicable when NVC is used.
NVC by default uses top.include and top.exclude files (where top representes the name of the top-level unit name) in the project root.
Every signal in the design hierarchy is saved to build/signals.nvc gtkwave save file with wf-% target.
- cadr: cadr and icmem components based on CADR schematics (
cadr.rename,icmem.rename: net renames applied while generating) - cadr1: busint components based on CADR1 schematics (
busint.rename) - cadr_test: testbenches for cadr pages (ALU, npc, PROM contents)
- cosim_vhpi: VHPI cosimulation sources for NVC
- cosim_vpi: VPI cosimulation sources for GHDL
- dip: dip components used by cadr, icmem and busint components
- doc: various documents and resources
- helper: non-CADR components required to run cadr_tb
- rom: ROM files loaded to CADR (P)ROMs and RAMs, and the generic-map tables
- scripts: utility scripts
- soap: soap4, the SUDS drawing to VHDL netlist extractor (soap.c and unpack.c are the originals, kept for reference)
- ghdl-uart: an experiment with a UART over a pty in GHDL, not part of the build
- ttl: ttl components used by dip components
- CLAUDE.md: the project rules for Claude Code (.claude/ holds local settings and is ignored)
Each folder have a README.md containing more information.
- work.cadr_book: cadr components
- work.icmem_book: icmem components
- work.busint_book: busint components
- work.dip: dip components
- work.amd,ecc,fairchild,intel,signetics,sn74,other: ttl components
- work.misc: misc functions and procedures (no components)