Wire Bundles/Ports

[amstan]

Sometimes parts have pins that belong to groups (ex: SPI, SDIO). Those pins shouldn't really force the user to connect each pin individually, but there should be a way to handle the connections in a group.

Example:

NetBundle("SPI_FLASH_") << mcu.SPI1 >> flash.spi

Instead of:

Net("SPI_FLASH_MOSI") << mcu.SPI1_MOSI >> flash.MOSI
Net("SPI_FLASH_MISO") >> mcu.SPI1_MISO << flash.MISO
Net("SPI_FLASH_CLK") << mcu.SPI1_CLK >> flash.CK
Net("SPI_FLASH_CS") << mcu.SPI1_CS >> flash.CS_L

More mockups to follow.