Name		Name	Last commit message	Last commit date
.gitignore		.gitignore
Makefile		Makefile
README.md		README.md
bram.sv		bram.sv
branch_feeder.sv		branch_feeder.sv
broadcast.sv		broadcast.sv
extract_a1h8.sv		extract_a1h8.sv
extract_a8h1.sv		extract_a8h1.sv
extract_v.sv		extract_v.sv
feed.sv		feed.sv
fifo.sv		fifo.sv
flip.sv		flip.sv
flip_8bit.sv		flip_8bit.sv
flip_8bit_half.sv		flip_8bit_half.sv
flip_impl.sv		flip_impl.sv
flip_v2.sv		flip_v2.sv
gather.sv		gather.sv
gen_test_flip8.cpp		gen_test_flip8.cpp
gen_test_flip_v2.cpp		gen_test_flip_v2.cpp
gen_test_pipeline.cpp		gen_test_pipeline.cpp
iv_sim.sv		iv_sim.sv
next_bit_pos.sv		next_bit_pos.sv
pipeline.sv		pipeline.sv
popcount.sv		popcount.sv
popcount_8bit.sv		popcount_8bit.sv
processer_sim.sv		processer_sim.sv
reversi.cpp		reversi.cpp
reversi.hpp		reversi.hpp
shift64.sv		shift64.sv
test_broadcast.sv		test_broadcast.sv
test_fifo.sv		test_fifo.sv
test_flip8.sv		test_flip8.sv
test_flip_v2.sv		test_flip_v2.sv
test_gather.sv		test_gather.sv
test_top.sv		test_top.sv
upper_bit.sv		upper_bit.sv

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FPGAOthello

Endgame solver of Othello, on FPGA

Top level design: pipeline.sv
Simulation design: processer_sim.sv

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Othello solver on FPGA

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