Build software better, together

eugene-tarassov / vivado-risc-v

Star

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

linux fpga boom riscv xilinx vivado risc-v nexys-video vc707 rocketchip genesys2 kc705 arty-a7

Updated Jul 13, 2026
Tcl

viktor-nikolov / MicroBlaze-DDR3-tutorial

Star

Tutorial of a HW design of MicroBlaze using DDR3 RAM on Arty A7 board; DDR3 RAM speed test application

fpga microblaze arty-a7

Updated Mar 21, 2026
C

hex-five / multizone-fpga

Star

This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 is Hex Five's official reference HW platform for its MultiZone Trusted Execution Environment and MultiZone Trusted Firmware. The X300 is an enhanced secure version of the SiFive's Freedom E300 built around the Rocket chip developed at U.C. Berkeley.

fpga rocket-chip xilinx fpga-soc risc-v xilinx-fpga bitstream digilent e300 sifive artix-100t sifive-freedom arty-a7 artix-35t

Updated Jan 23, 2024
Scala

Thraetaona / Innervator

Sponsor

Star

Innervator: Hardware Acceleration for Neural Networks

open-source machine-learning fpga paper vhdl standalone dnn artificial-intelligence neural-networks neuron vlsi hardware-acceleration xilinx-fpga artifical-neural-network freestanding arty-a7 vhdl-2008 ieee-1076 hardware-compiler

Updated Aug 3, 2024
VHDL

HafizMutahirAhmed / RV32I-5-Stage-Processor

Star

A fully pipelined 5-stage RV32I processor implemented in SystemVerilog. This design models instruction-level parallelism with forwarding and hazard detection, and passes all RISCOF compliance tests for the RV32I base ISA.

processor-architecture fpga processor riscv rtl vivado systemverilog hdl risc-v rv32i verilator processor-design fpga-programming arty-a7 risc-v-architecture five-stage riscof pipelined-processor rv32i-processor

Updated Jul 27, 2025
SystemVerilog

Luke7412 / IpLibrary

Star

Library containing various VHDL IPs

rtl ip xilinx vivado ip-xact systemverilog ipxact arty-a7 packaged-ip

Updated Jan 5, 2024
SystemVerilog

vohoangnguyennnn / smart-parking-fpga-AI

Star

RTL-based smart parking controller with UART protocol, FPGA verification, ESP32 gateway and AI license plate recognition integration

ai fpga esp32 verilog systemverilog system-design arty-a7 microphase

Updated Jul 1, 2026
SystemVerilog

timothystotts / fpga-serial-acl-tester-3

Star

A small FPGA and APSoC project of different implementations for testing Measurement and Activity Events of a SPI accelerometer. Refresh of fpga-serial-acl-tester-1 and -2.

fpga vhdl verilog systemverilog pmod zybo-z7 arty-s7 arty-a7 systemonchip

Updated Aug 10, 2024
Tcl

timothystotts / fpga-serial-mem-tester-3

Star

A small FPGA and APSoC project of different implementations for testing byte-by-byte a serial flash. Refresh of fpga-serial-mem-tester-1 and -2.

fpga vhdl systemverilog pmod zybo-z7 arty-s7 arty-a7 systemonchip

Updated Aug 10, 2024
Tcl

Luke7412 / IpDemonstrators

Star

Vivado demonstrator projects for IPs in IpLibrary repo.

fpga systemverilog demos xilinx-vivado arty-a7

Updated Dec 13, 2023
Python

riccardonicolaidis / Sampler_Pmod_AD1

Star

Implementation of a sampler using the XADC mounted on the Arty A7-35T development board and the PmodAD1 by Digilent (AD7476A).

fpga vhdl xilinx adc vivado verilog-hdl digilent pmod analog-to-digital-converter arty-a7

Updated Apr 2, 2022
VHDL

riccardonicolaidis / PmodSD_Arty_A7_Project

Star

In this project I wanted to implement a microprocessor on an FPGA with the ability to write files onto an SD card (micro SD in particular) exploiting the Arty A7 development board and the Digilent PModSD.

fpga hardware verilog vivado sd-card digilent starting-template vitis arty-a7

Updated May 3, 2022
VHDL

rtbnb / SixteenShadesOfCpu

Star

A 16-bit RISC CPU implemented in VHDL on an Arty A7-35T development board

cpu fpga vhdl risc 16bit arty7 soft-cpu arty-a7

Updated Feb 7, 2025
VHDL

vohoangnguyennnn / fpga-uart-esp32

Star

UART communication between ESP32 and FPGA to control LEDs (Verilog + Embedded C)

fpga esp32 verilog uart-protocol arty-a7

Updated Apr 25, 2026
Verilog

namangoyal-work / fpga-tick-to-trade

Star

Deterministic, formally verified tick-to-trade engine in FPGA fabric — 5-cycle latency, zero CPU, proven fail-closed. SystemVerilog on Arty A7.

fpga trading low-latency ethernet systemverilog formal-verification cocotb symbiyosys hardware-design arty-a7

Updated Jul 5, 2026
SystemVerilog

infinitexplore / sinc-resampler

Star

Audio Sinc Resampler in Chisel

fpga chisel resampler sinc arty-a7

Updated Jun 2, 2026
Scala

riccardonicolaidis / project_getting_started_Vivado_Vitis

Star

Personal revision of the tutorial "Getting started with Vivado and Vitis for Baremetal system" by Digilent.

fpga xilinx vivado hdl digilent vitis arty-a7

Updated Mar 29, 2022
VHDL

riccardonicolaidis / Particle-Detector-ARTY-A7

Star

Implementation of a particle detector using a cheap FPGA developement board. The FPGA exploits some ADCs and then if there are coincidences in the signals, the event is recorded.

fpga detector verilog systemverilog particle-physics arty-a7

Updated Apr 12, 2024
VHDL

marcosluz36 / GEMM_Accelerator

Star

Generic Multiplication Accelerator on FPGA

ethernet systemverilog xilinx-vivado arty-a7 systolic-array

Updated Jun 22, 2026
Verilog

pranav0x2212 / RTOSsseract

Star

RTOS for MicroBlaze on Arty A7-35T with basic tasking and peripheral support

embedded-systems rtos arty-a7

Updated Apr 14, 2025
C

Navigation Menu

arty-a7

Here are 34 public repositories matching this topic...

eugene-tarassov / vivado-risc-v

viktor-nikolov / MicroBlaze-DDR3-tutorial

hex-five / multizone-fpga

Thraetaona / Innervator

HafizMutahirAhmed / RV32I-5-Stage-Processor

Luke7412 / IpLibrary

vohoangnguyennnn / smart-parking-fpga-AI

timothystotts / fpga-serial-acl-tester-3

timothystotts / fpga-serial-mem-tester-3

Luke7412 / IpDemonstrators

riccardonicolaidis / Sampler_Pmod_AD1

riccardonicolaidis / PmodSD_Arty_A7_Project

rtbnb / SixteenShadesOfCpu

vohoangnguyennnn / fpga-uart-esp32

namangoyal-work / fpga-tick-to-trade

infinitexplore / sinc-resampler

riccardonicolaidis / project_getting_started_Vivado_Vitis

riccardonicolaidis / Particle-Detector-ARTY-A7

marcosluz36 / GEMM_Accelerator

pranav0x2212 / RTOSsseract

Add this topic to your repo