(WIP) NES emulator running on FPGA implemented in scala(w/ chisel)
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Apr 24, 2022 - Verilog
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de0-cv
Here are 5 public repositories matching this topic...
Controle de motor DC + Sensores fim de curso implementado em VHDL para o kit DE0-CV utilizado na matéria de Elementos de sistemas do 3 semestre de Engenharia da computação do Insper.
fpga robo altera vhd l298n l298 altera-fpga l298n-h-bridge engenharia-de-computacao insper de0 de0cv de0-cv robot-fpga robo-fpga
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Nov 1, 2019 - VHDL
Configurable PWM generator implemented in SystemVerilog on a DE0-CV FPGA with self-checking verification
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Sep 6, 2026 - SystemVerilog
Team 21 - Mini-Project
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Jul 30, 2024 - VHDL
FSM-driven password authentication in Verilog RTL - verified in ModelSim, synthesized in Quartus, and tested on a DE0-CV FPGA.
fsm fpga verilog computer-architecture modelsim testbench digital-design lfsr quartus functional-verification rtl-design de0-cv
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Aug 26, 2026 - Verilog
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