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ece-project

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Designed and analyzed a CMOS-based 6T SRAM cell using Cadence Virtuoso and Spectre Simulator. Performed DC and transient analyses, evaluated Voltage Transfer Characteristics (VTC) and Static Noise Margin (SNM), and studied hold, read, and write operations to assess memory cell stability and performance.

  • Updated Jul 31, 2026
  • Verilog

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