#
hitsz
Here are 24 public repositories matching this topic...
Verilog miniRV/RISC-V style CPU course project featuring single-cycle and five-stage pipeline designs with hazard handling.
cpu pipeline verilog computer-architecture risc-v digital-design computer-organization cpu-design hitsz
-
Updated
Jun 16, 2026 - Verilog
An automated line-following car project for the 2022 AUTO1001 course at HITSZ.
-
Updated
Jul 23, 2025 - C++
哈尔滨工业大学（深圳）中文 LaTeX 简历模板，支持 XeLaTeX 与 Overleaf
-
Updated
Jul 18, 2026 - TeX
Add this topic to your repo
To associate your repository with the hitsz topic, visit your repo's landing page and select "manage topics."