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mips-cpu

Here are 15 public repositories matching this topic...

lvyufeng / step_into_mips

一步一步写MIPS CPU

verilog mips-cpu nscscc

Updated Jun 5, 2026
Verilog

yuxincs / MIPS-CPU

A Simulative MIPS CPU running on Logisim.

circuit logisim mips-cpu mips-instructions pipeline-cpu

Updated Jul 17, 2022
Assembly

Jed-Z / computer-organization-lab

中山大学计算机组成原理实验 (2018 秋)：用 Verilog 设计并实现的简易单周期和多周期 CPU

cpu verilog-hdl sysu mips-cpu cpu-designs

Updated Mar 21, 2021
Verilog

martinKindall / mips_cpu

Single Cycle 32 bit MIPS

fpga mips systemverilog basys3 mips-cpu single-cycle basys3-fpga single-cycle-processor

Updated Dec 24, 2022
SystemVerilog

Li-Jinsong / MIPS-Single-39

MIPS单周期CPU，共支持39条指令

cpu mips mips32 mips-cpu

Updated Feb 3, 2023
Verilog

RenzoTsai / MyCPU

A Five Stage MIPS CPU for UCAS Computer Architecture Module

mips-cpu

Updated Nov 27, 2019
Assembly

akira2963753 / mips-5stage-cpu

This is NTUST-EE 2025 Computer Organization, the course's final project is the implementation of the 5-stage pipelined cpu based on mips.

cpu mips-processor mips-cpu computer-organisation-architechure 5-stage-pipelined-processor

Updated Mar 16, 2026
Verilog

arashsm79 / mips-hdl

Single-cycle and multi-cycle implementation of a subset of MIPS instruction set

mips assembly verilog hdl mips-architecture mips-cpu single-cycle multi-cycle cpu-design

Updated Jul 8, 2022
Verilog

ashvah / cpu-pipelining

Implement a MIPS 5-stage pipelined CPU using Vivado

pipeline vivado mips-cpu

Updated Mar 4, 2022
Verilog

PngWnA / MIPS-CPU

Computer Architecture: Simple MIPS CPU implementation in course

cpu computer-architecture mips-cpu

Updated Oct 29, 2025
VHDL

MahmoudAlQataa / Single-Cycle-MIPS-CPU-Logisim

Single-cycle 32-bit MIPS CPU designed and simulated in Logisim, built for the Computer Architecture Lab (LCOM 3010) at the Islamic University of Gaza. Supports lw, sw, add, sub, and, or, slt, beq, and j.

mips assembly university-project digital-logic computer-architecture logisim digital-design mips-cpu cpu-design single-cycle-cpu

Updated Jul 25, 2026

samuel-adekunle / MIPS_cpu

Verilog MIPS Processor

verilog mips-cpu

Updated Dec 21, 2020
Verilog

junqi-xie / MIPS-CPU

The lab project for ICE2603 (2021 Spring): A pipelined MIPS CPU on an FPGA board

fpga computer-systems mips-cpu

Updated May 28, 2021
Verilog

sShahriyaryG / pipelined-mips-cpu-verilog

A simplified 5-stage pipelined MIPS CPU implemented in Verilog with hazard handling, forwarding, flushing, cache behavior, and simulation testbench.

cpu verilog vivado digital-logic pipelining computer-architecture mips-architecture mips-cpu pipeline-cpu cpu-simulator hardware-design

Updated Jun 2, 2026
Verilog

xiaoyoumi9924 / logisim-mips-cpu

手搓cpu，基于logisim软件制作，包含了从时序电路搭建到五级流水线MIPS cpu，适用于吉林大学计算机硬件系统实验一课程

pipeline mips logisim computer-organization mips-cpu cpu-design

Updated Sep 12, 2026
PowerShell

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