netlist

draws an SVG schematic from a JSON netlist

HAL – The Hardware Analyzer

PCB Design Language: A programming way to design schematics.

Netlist API (and more) for EDA flow development

Tools for working with circuits as graphs in python

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

A hand-drawn schematic sketch recognizer and converter. Three-Step pipeline: Component detection using traditional image processing; Component classification using a custom trained CNN; Schematic generation using a proprietary generation algorithm.

A mixed signal netlist language (pre-alpha)

Give AI agents the power to read Cadence, Altium, and KiCad designs

A standalone structural (gate-level) verilog parser

This guide will teach you all the basics of KiCad from schematic building to PCB design. It will also teach you how to add libraries, create your own symbols & footprints, export the drill and gerber files, and many more tips to get you started on your KiCad journey!

SPICE netlists parser for .NET

A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).

A MATLAB project that uses modified nodal analysis to calculate the node voltages of any analog circuit.

The code about TC-Bench and CircuitMind

MCP server for AI agents to explore SystemVerilog/Verilog netlists: trace connectivity, walk hierarchy, jump to source - without pasting RTL into context. Built on najaeda.

This is a SpyDrNet Plugin for a physical design related transformations

An Open Source EDA Infracstructure and Tools from Netlist to GDS for ASIC Design.

TMR utilities for the SpyDrNet project

This is a demo for still image compression application