ring-oscillator

🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

Repository to store all design and testbench files for Senior Design

Parameterized Ring Oscillator and Testbench. The design is written in Verilog and testbench is developed in SystemVerilog.

Ring oscillator and its application as Physical Unclonable Function (PUF) for password management

Implementation of a Ring Oscillator-based Physically Unclonable Function (PUF) in Sky130, with 8 bits of Challenge-Response Pairs (CRP)

Comprehensive Random Number Generator implementation featuring both Pseudo-Random Number Generator (PRNG) using Linear Feedback Shift Registers and True Random Number Generator (TRNG) using Ring Oscillators

This project implements a tetrahedral oscillator inspired by the paper “Analysis and Design of a Tetrahedral Oscillator” by Richelle L. Smith and Thomas H. Lee. The oscillator is built from coupled inverter pairs, and its operating frequency is tuned by adding capacitive loads to the internal nodes.

Verilog and FPGA implementations of clock generators and a divide-by-113 frequency divider with ModelSim and Quartus results.

All the source files related to the design and simulation of a Ring Oscillator and a Programmable Logic Device(PLD) using the LTSpice XVII simulator for UOM's EN2110 - Electronics - III Module ❄

LTspice simulations of ring, NE555 astable and Schmitt-trigger oscillators with measured timing and frequency analysis.

FuzzyMSFLA-Algorithm (Fuzzy adaptive optimisation method)

Two-tile all-digital PLL taped out on TinyTapeout SKY26c (SkyWater 130nm). Ring-oscillator DCO, counter-based TDC, PI loop filter. Locks 10 MHz reference to programmable output frequency up to 63x.

Voltage Controlled Oscillator that produces 1GHz output frequency at voltage 3.3V using IHP PDK as a part of eSim Marathon

Ring oscillator subcircuits

VHDL ring-oscillator PUF (ROPUF) designed in Xilinx Vivado, simulated, synthesized, and tested on physical FPGA hardware.

Study of deep correlations in (pseudo) random bits.

The fabricated CORDIC-1, rebuilt on a standard-cell library I designed myself: device physics, transistor sizing, cell layouts and ngspice-to-Liberty characterization all mine. Same RTL bit for bit, so the shuttle chip is the control group. On-die ring oscillators report my own cells' propagation delay in real silicon. Sky130 / TinyTapeout.

90 nm positive-feedback OTA ring-VCO research with architecture screening, practical current mirrors and tuning-range analysis.

Cadence Virtuoso project of 5-stage ring oscillator

Ring-oscillator PLL IP for IHP SG13CMOS5L (SG13G2) — Chipalooza Challenge