An attempt at a small Verilog implementation of the original Apple 1 on an FPGA
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Updated
Sep 22, 2025 - Verilog
An attempt at a small Verilog implementation of the original Apple 1 on an FPGA
Fairly simple example of 8-color VGA text generation in SystemVerilog for UPduino FPGA
Evaluating per particle performance of accelerated and non-accelerated particle filtering on embedded hardware.
Example to test all UPduino GPIO outputs
Desarrollo en Verilog, proyecto de KiCad e informe del Trabajo Práctico N° 2 de 22.13 - Electrónica III. Implementación de calculadora en FPGA.
UPduino 3.x: new 4 layer layout, various other improvements
Educational FPGA lab board for the UPduino v3.1. Switches, LEDs, 7-segment display, VGA, R-2R DAC, ADC and WS2812 behind shift-register scan chains, with a Verilog BSP and worked examples.
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