uvm

cocotb: Python-based chip (RTL) verification

Functional verification project for the CORE-V family of RISC-V cores.

Fun, portable, minimalistic virtual machine.

AMBA AXI VIP

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Code generation tool for control and status registers

Awesome ASIC design verification

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Network on Chip Implementation written in SytemVerilog

Control and status register code generator toolchain

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

VIP for AXI Protocol

Kho tài liệu đi từ nền tảng Điện tử căn bản đến Thiết kế vi mạch, tập trung vào Front-End (RTL/DV). Tích hợp kiến thức bổ trợ cho các hướng công việc khác thuộc chuyên ngành Điện Tử. Biên soạn bởi Minh Ú (Phùng Quang Minh).

System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment

INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.

A Framework for Design and Verification of Image Processing Applications using UVM

Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.

Open-source, evidence-driven MCP server for RTL simulation debugging: correlate VCS/Xcelium logs, VCD/FSDB waveforms, SystemVerilog/UVM source, hierarchy, and connectivity to trace failures to root cause.

DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision