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@vyges-ip

Vyges - IP Catalog

Curated, metadata-first silicon IP catalog maintained by Vyges. Open and commercial IP packaged for composable SoC generation
README.md

Vyges IP Catalog

Open registry for silicon IP — metadata-first, machine-readable, free for the field.

vyges-ip hosts the public mirror of the Vyges silicon IP registry. Each repo is a single IP block packaged with a consistent vyges-metadata.json describing ports, parameters, dependencies, integration hints, and license terms. The index lives in vyges-ip-catalog.

Operator

vyges-ip is operated by TrustStix Inc (California, USA — C Corporation). The registry itself is free and open; operational costs (hosting, indexing, curation) are absorbed by TrustStix. We treat the catalog as public infrastructure for the silicon ecosystem.

If your team uses VyCatalog and wants to support open-silicon infrastructure, GitHub Sponsors is being enabled — see the Sponsor link on this page. Sponsorships are processed by TrustStix Inc and are not tax-deductible.

Links

Popular repositories Loading

  1. ibex ibex Public

    Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

    SystemVerilog 1

  2. opentitan-kmac opentitan-kmac Public

    Keccak Message Authentication Code (KMAC) and Secure Hashing Algorithm 3 (SHA3)

    SystemVerilog 1

  3. caliptra-kmac caliptra-kmac Public

    SHA-3/SHAKE/cSHAKE/KMAC Keccak-based hash and MAC engine with optional DOM masking. From CHIPS Alliance Caliptra Root of Trust.

    SystemVerilog 1

  4. sky130-sar-adc sky130-sar-adc Public

    Silicon-proven 12-bit fully-differential SAR-ADC in SKY130

    Verilog 1

  5. sky130-delta-sigma-adc sky130-delta-sigma-adc Public

    12-bit 10-KSPS incremental delta-sigma ADC in SKY130

    Verilog 1

  6. coralnpu-subsystem coralnpu-subsystem Public

    CoralNPU full SoC Chisel subsystem — crossbar, peripherals (GPIO, SPI, CLINT, DMA), DDR bridges. Generated from Chisel.

    SystemVerilog 1

Repositories

Showing 10 of 162 repositories
  • vyges-ip-catalog Public

    Auto-synced cache of every vyges-metadata.json from the vyges-ip org. Single source of truth for downstream tooling.

    vyges-ip/vyges-ip-catalog's past year of commit activity
    Python 0 0 0 0 Updated Sep 20, 2026
  • ibex Public

    Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

    vyges-ip/ibex's past year of commit activity
    SystemVerilog 1 Apache-2.0 0 0 0 Updated Sep 17, 2026
  • tech_cells_generic Public

    Technology-dependent cells for generic process (simulation/FPGA) — Vyges catalog mirror of pulp-platform/tech_cells_generic. Dependency of pulp-riscv-dbg + many PULP IPs.

    vyges-ip/tech_cells_generic's past year of commit activity
    SystemVerilog 0 0 0 0 Updated Sep 17, 2026
  • pulp-riscv-dbg Public

    RISC-V Debug Module (pulp-platform/riscv-dbg) — Vyges catalog mirror. Lightweight alternative to opentitan-rv-dm for space-constrained SoCs without OpenTitan lifecycle/alert infrastructure.

    vyges-ip/pulp-riscv-dbg's past year of commit activity
    SystemVerilog 0 0 0 0 Updated Sep 17, 2026
  • common_cells Public

    Common SystemVerilog components (FIFOs, CDC, arbiters, counters) — Vyges catalog mirror of pulp-platform/common_cells. Dependency of pulp-riscv-dbg + many PULP IPs.

    vyges-ip/common_cells's past year of commit activity
    SystemVerilog 0 0 0 0 Updated Sep 17, 2026
  • opentitan-aon-timer Public

    Always-On ("AON") Timer

    vyges-ip/opentitan-aon-timer's past year of commit activity
    SystemVerilog 0 0 0 0 Updated Sep 14, 2026
  • caliptra-tlul Public

    Caliptra IP: caliptra-tlul (extracted from chipsalliance/caliptra-rtl)

    vyges-ip/caliptra-tlul's past year of commit activity
    SystemVerilog 0 0 0 0 Updated Sep 14, 2026
  • opentitan-spi-host Public

    Serial Peripheral Interface (SPI) is a synchronous serial interface, commonly used for NOR flash devices and off-chip peripherals such as ADCs, DACs, or temperature sensors.

    vyges-ip/opentitan-spi-host's past year of commit activity
    SystemVerilog 0 0 0 0 Updated Sep 14, 2026
  • opentitan-tlul Public

    TL-UL is a lightweight (uncached) bus that combines the point-to-point split-transaction features of the powerful TileLink (or AMBA AXI) 5-channel bus without the high pin-count overhead.

    vyges-ip/opentitan-tlul's past year of commit activity
    SystemVerilog 0 0 0 0 Updated Sep 14, 2026
  • opentitan-lc-ctrl Public

    Life Cycle Controller

    vyges-ip/opentitan-lc-ctrl's past year of commit activity
    SystemVerilog 0 0 0 0 Updated Sep 14, 2026
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