uart-tx

Must-have verilog systemverilog modules

Serial communication (USART) on the ATMega 2560 using C++ classes

FPGA implementation for UART interface for rx/tx data with support AXI-Stream protocol

Cross-platform UART debugging and log analysis for embedded and firmware developers.

Basic continous integration testing for verilog projects

ESP32-iUART (WROOM-32)

Basys 3 UART Tx for COMPE470L class

300 baud 8N1 UART transmitter with limited character set (0x40..0x5F) loading as ASIC design

Deterministic ARM Cortex-M4 (STM32) firmware and PyQt6 Ground Station with Saleae HIL verification.

milestone-1-communicating-with-will-byers-kvl-fan-club created by GitHub Classroom

A complete VHDL UART transceiver and loopback interface featuring 2-stage input synchronization, mid-bit oversampling, framing error detection, and an integrated FIFO buffer.

Keyboard Scanner, UART Tx -(nandland.com), Sipo_Reg, Switch Debounce(counter), Linear Feedback Shift Register, DiceGame(2 player,win on eqauality).

verilog-uart

esp8266

Design of Universal Asynchronous Receiver Transmitter Interface using verilog HDL

FSM tabanlı, VHDL ile kodlanmış UART TX modülü. Vivado kullanılarak tasarlanmış ve FPGA üzerinde seri veri iletimi için geliştirilmiştir.

Dynamixel xl320 support for ESP boards with micropython.

UART transmitter and receiver in Verilog with a self-checking testbench