uart-receiver

Must-have verilog systemverilog modules

Serial communication (USART) on the ATMega 2560 using C++ classes

UART receive task

Low resource UART receiver for FPGA.

Cross-platform UART debugging and log analysis for embedded and firmware developers.

Universal Asynchronous Receiver Transmitter

Projekt (UART přijímací část) z předmětu Návrh číslicových systémů (INC), druhý semestr bakalářského studia BIT na FIT VUT/BUT, ak.rok 2021/2022

Contents presented in the Microcontrollers Laboratory Course; Microcontrollers used: Arduino UNO R3 & DOIT ESP32 DEVKIT V1 - CSE Department, Shiraz University, Spring 2025

A parametrizable, modular UART with FIFO buffers, even parity, and interrupt support.

This is an ESP32 project for receiving json from another device by uart and send it to the server. Also provide web service for management.

SystemVerilog UART transciever

UART (Universal Asynchronous Receiver-Transmitter) is a widely used,, cost-effective serial communication protocol that facilitates data exchange between microcontrollers and peripheral devices using only two wires—Transmit (TX) and Receive (RX). It operates asynchronously, meaning it relies on matched baud rates rather than a shared clock signal

An Android app built with Kotlin and Jetpack Compose to talk to microcontrollers and serial hardware over a standard USB OTG cable.

Verilog HDL implementation, simulation, and functional verification of a UART Transmitter and Receiver using Intel Quartus Prime and ModelSim.

Phase-2 Cycle-1: RTL Protocol Foundations

Serial dashboards and control-loop sandboxes, no GUI code. Showcase repo — source available on request.

UART transmitter and receiver in Verilog with a self-checking testbench

A complete UART (Universal Asynchronous Receiver/Transmitter) implementation for FPGAs, written in Verilog HDL. This project includes transmitter and receiver modules, baud rate generation, and test infrastructure for both simulation and hardware validation.